This invention relates in general to clock tree schemes in semiconductor dies and in particular to a distributed clock tree scheme for reducing the die area occupied by the clock tree while reducing clock skew and inductance of the clock tree connection.
Clock signals are required for the operation of many circuits fabricated on semiconductor dies. In integrated circuits, clock signals are frequently required for the operation of many circuits located on different parts of the semiconductor die. For this reason, the conventional scheme for routing the clock signal for these different parts of the die is to fabricate an electrically conductive clock tree spine on the die surface driven by means of a clock pad as shown if FIG. 1.
FIG. 1 is a top view of a portion of a semiconductor chip package illustrating a conventional clock tree scheme. As shown in FIG. 1, package 10 includes a semi-conductor die 12 and a number of electrically conducting bond posts (collectively labelled 14) surrounding the die. In a ceramic package, the group of bond posts 14 would be located on top of a ceramic surface inside the package. In a plastic package, bond posts 14 would form a portion of a leadframe (not shown) or form conductive traces on top of a substrate for supporting the die 12. At the edge of the die surface are a number of pads 16 suitable to be connected to one of the bond posts 14. Each of the pads may be electrically connected to one of the bond posts by means of a bonding wire so that electrical circuits fabricated in the die and electrically connected to the pads may be accessed for input/output functions through the bond posts connected to the pads as in a manner known to those skilled in the art. One of the pads at the edge of the die is a clock pad 18, used for driving a clock signal down the clock tree spine 20.
As shown in FIG. 1, clock tree spine 20 has a main clock line 22 and a number of tributaries 24 connected electrically to the main line 22 as shown in FIG. 1. Clock pad 18 is electrically connected to the main line 22. The clock tree spine 20 and clock pad 18 may be simply formed as a single metal layer in a process. A bonding wire 32 connects the clock pad 18 to one of the posts 14a. In this manner, a clock signal fed to post 14a will pass through wire 32 to clock pad 18. Clock pad 18 may be of a conventional construction. Any number of clock input pads may be used. One example is VLSI Macro No. PC6C04 which is a CMOS inverting clock input pad with 4X driver. Incorporated by reference are data sheets on PC6C04, a copy of which is attached. Analogous clock input pads are available from other vendors such as LSI Logic.
The driver of the clock pad drives the clock signal fed to it through finger 14a and bonding wire 32 down the main clock line 22 and to the tributaries 24. In this manner, the clock signal fed to package 10 is supplied to different areas of the die 12. The clock signal is then available at different parts of the chip or die for connection to and operation of circuits on different parts of the die. The clock tree spine 20 itself has a certain capacitance and resistance. Therefore, when the clock signal is driven down the spine by pad 18, the clock signal will encounter a delay when it travels down the spine from pad 18. In other words, the clock signal taken at the end of this main clock line 22, such as at point b, will be delayed relative to the clock signal taken from a point upstream, such as at point a. Even for small dies, the distance between points a and b can be as much as 500 mils, resulting in the delay of the order of 1 nanosecond. This is known as clock skew which is undesirable since it introduces a delay between the clock signals used for operating different circuits on the same die.
One solution for reducing clock skew which has been used in conventional design is to use a thicker main clock line. A thicker clock line reduces the resistance of the line and therefore reduces the delay caused by the line and the resulting clock skew. Increasing the width of the clock line has the disadvantage of taking up more precious real estate on the die surface. It is therefore desirable to provide a clock tree scheme whereby width of the clock tree spine needed is reduced while maintaining an acceptable clock skew or even reducing clock skew.